This invention relates to a system clock generator included in a low power consumption CMOS one-chip microcomputer.
For example, a one-chip microcomputer having a timekeeping function includes a circuit such as an oscillator and a timekeeping counter which requires clock signals whether the system is in operation or in a ready state and other circuits which do not require clock signals especially when the system is in the ready state. In this manner, clock signals useful in achieving an intended purpose through the utilization of a microcomputer can be classified into two categories, that is, ones which work even when the system is in the ready state and ones which are to be interrupted during the ready state of the whole system.
FIG. 1(a) shows a prior art system clock generator wherein clock signals .phi..sub.01 ', .phi..sub.02 ' and .phi..sub.03 ' developed from a basic clock generator A.sub.0 work during the ready state of the system. By controlling gate circuits B.sub.1 -B.sub.3 with a system control signal S with regard to these clock signals, there are developed different clock signals .phi..sub.01, .phi..sub.02 and .phi..sub.03 which are interrupted during such ready state. FIG. 1(b) shows a circuit for creating the system control signal S, which circuit includes a dynamic circuit E responsive to the clock signals .phi..sub.01 ', .phi..sub.02 ' and .phi..sub.03 '. To this end, even while the system is in the ready state, circuits related with the clock signals .phi..sub.01 ', .phi..sub.02 ' and .phi..sub.03 ' work at all times, for example, the circuit E included in the system cntrol signal generator. This is unfavorable from the viewpoint of power saving.